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Commit in GeomConverter/test/org/lcsim/geometry/subdetector on MAIN
SiStripTrackerBarrelTest.xml+78-111.3 -> 1.4
JM: Add the VXD to the SiStripTrackerBarrel test case XML.

GeomConverter/test/org/lcsim/geometry/subdetector
SiStripTrackerBarrelTest.xml 1.3 -> 1.4
diff -u -r1.3 -r1.4
--- SiStripTrackerBarrelTest.xml	29 Sep 2006 22:53:45 -0000	1.3
+++ SiStripTrackerBarrelTest.xml	3 Oct 2006 00:06:40 -0000	1.4
@@ -11,7 +11,7 @@
 		<constant name="world_z" value="world_side"/>
 
 		<constant name="tracking_region_radius" value="180.0 * cm"/>
-		<constant name="tracking_region_zmax" value="0.1 * cm"/>
+		<constant name="tracking_region_zmax" value="300.0 * cm"/>
 	</define>                                                                       
 	<materials>
     </materials>
@@ -20,12 +20,82 @@
 	</display>
 	<detectors>
 	
-		<detector id="1" name="SiStripTrackerBarrel" type="SiStripTrackerBarrel" readout="SiStripTrackerBarrel_RO" vis="TestVis">
+		<detector id="1" name="VtxBarrel" type="SiStripTrackerBarrel" readout="VtxBarrel_RO" vis="TestVis">
+
+			<module name="VtxBarrelModuleInner">
+				
+				<module_envelope width="9.8" length="63.0 * 2" thickness="0.6" />
+				
+				<module_component  width="7.6" length="125.0" thickness="0.26" material="CarbonFiber" sensitive="false"> 
+					<position z="-0.08"/>
+				</module_component>
+				
+				<module_component  width="7.6" length="125.0" thickness="0.05" material="Epoxy" sensitive="false"> 
+					<position z="0.075"/>
+				</module_component>
+				
+				<module_component  width="9.6" length="125.0" thickness="0.1" material="Silicon" sensitive="true"> 
+					<position z="0.150"/>
+				</module_component>
+				
+			</module>
+
+			<module name="VtxBarrelModuleOuter">
+			
+				<module_envelope width="14.0" length="126.0" thickness="0.6" />
+				
+				<module_component  width="11.6" length="125.0" thickness="0.26" material="CarbonFiber" sensitive="false"> 
+					<position z="-0.08"/>
+				</module_component>
+				
+				<module_component  width="11.6" length="125.0" thickness="0.05" material="Epoxy" sensitive="false"> 
+					<position z="0.075"/>
+				</module_component>
+				
+				<module_component  width="13.8" length="125.0" thickness="0.1" material="Silicon" sensitive="true"> 
+					<position z="0.150"/>
+				</module_component>				
+				
+			</module>			
+			
+			<layer module="VtxBarrelModuleInner" id="1">
+				<barrel_envelope inner_r="13.0" outer_r="17.0" z_length="63 * 2" />
+				<rphi_layout phi_tilt="0.0" nphi="12" phi0="0.2618" rc="15.05" dr="-1.15" />
+				<z_layout dr="0.0" z0="0.0" nz="1" />
+			</layer>
+
+			<layer module="VtxBarrelModuleOuter" id="2">
+				<barrel_envelope inner_r="21.0" outer_r="25.0" z_length="63 * 2" />
+				<rphi_layout phi_tilt="0.0" nphi="12" phi0="0.2618" rc="23.03" dr="-1.13" />
+				<z_layout dr="0.0" z0="0.0" nz="1"/>
+			</layer>
+
+			<layer module="VtxBarrelModuleOuter" id="3">
+				<barrel_envelope inner_r="34.0" outer_r="38.0" z_length="63 * 2" />
+				<rphi_layout phi_tilt="0.0" nphi="18" phi0="0.0" rc="35.79" dr="-0.89" />
+				<z_layout dr="0.0" z0="0.0" nz="1"/>
+			</layer>
+
+			<layer module="VtxBarrelModuleOuter" id="4">
+				<barrel_envelope inner_r="46.6" outer_r="50.6" z_length="63 * 2" />
+				<rphi_layout phi_tilt="0.0" nphi="24" phi0="0.1309" rc="47.5" dr="0.81" />
+				<z_layout dr="0.0" z0="0.0" nz="1"/>
+			</layer>
+			
+			<layer module="VtxBarrelModuleOuter" id="5">
+				<barrel_envelope inner_r="59.0" outer_r="63.0" z_length="63 * 2" />
+				<rphi_layout phi_tilt="0.0" nphi="30" phi0="0.0" rc="59.9" dr="0.77" />
+				<z_layout dr="0.0" z0="0.0" nz="1"/>
+			</layer>			
+		
+		</detector>				
+	
+		<detector id="2" name="SiStripTrackerBarrel" type="SiStripTrackerBarrel" readout="SiStripTrackerBarrel_RO" vis="TestVis">
 		
 			<module name="SiTrackerModule">
 		
 				<module_envelope width="97.79" length="97.79" thickness="5.5"/>
-							
+	
 				<!--
 				<module_component  width="97.79" length="97.79" thickness="0.1" material="Kapton" sensitive="false">				
 					<position z="-2.692"/>
@@ -97,24 +167,21 @@
 				<z_layout dr="5.5" z0="1581.0" nz="37"/>
 			</layer>
 		
-		</detector>	
+		</detector>
+
 	</detectors>
 	<readouts>
 		<readout name="SiStripTrackerBarrel_RO">
 			<id>system:3,barrel:2,layer:4,phi:8,z:8,sensor:5</id>
 		</readout>
+		<readout name="VtxBarrel_RO">
+			<id>system:3,barrel:2,layer:4,phi:8,z:8,sensor:5</id>
+		</readout>
 	</readouts>
 	<fields>
    </fields>
 </lccdd>
-
-				<!--
-				<module_component zc="" width="97.79" length="97.79" thickness="" material="" sensitive="false" />
-				-->
 		
-						<!--<rphi_layout phi_tilt="0.19" nphi="1" phi0="0.01745" rc="1230.0" />
-				<z_layout dr="5.5" z0="1581.0" nz="1"/>-->
-	
 	<!--
 		<detector id="1" name="SiStripTrackerBarrel" type="SiStripTrackerBarrel" readout="SiStripTrackerBarrel_RO" vis="TestVis">
 			<module name="MyModule">
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